1. Field of the Invention
The present invention relates to a write compensation circuit and a signal interpolation circuit. The signal interpolation circuit of this invention receives a pair of input signals having different phases and outputs a pair of output signals each having a phase similar to that of the corresponding input signal and another output signal having a phase intermediate between the pair of output signals.
2. Description of the Related Art
Upon reproduction of data recorded in a recording device, peak shift of a reproduced waveform occurs. Among methods known for compensating the peak shift is a write compensation method in which when recording a particular bit sequence of data, the phase of a signal representing a prescribed bit is adjusted.
A write compensation circuit portion which carries out the write compensation method has a delay generating section including a plurality of delay circuits having a plurality of buffers. The delay generating section controls the number of buffers which are driven by the delay circuits and generates a plurality of delay signals. The write compensation circuit portion has a selector which selects one of the plurality of delay signals to generate a write clock and generates write data in response to the write clock.
“A 300 Mb/s BiCMOS EPR4 Read Channel for Magnetic Hard Disks”, pp. 378, 379, Proc. of IEEE, 1998, ISSCC, discloses a technique used for the delay generating section in the write compensation circuit portion, which utilizes VCO.
The delay amount of a clock can be held constant by means of the VCO technique in the delay circuit generating a write compensation amount. The stability of the delay amount can be protected from a source voltage change and variation in circuits caused by a temperature change and the like. When the VCO technique is applied to the delay generating section, additional circuits for compensating temperature and phase are required.
A signal interpolation circuit has been developed which receives a pair of waveform signals having a phase difference, and generates a plurality of waveform signals spaced equally in phase between the pair of waveform signals. “A Portable Digital DLL Architecture for CMOS Interface Circuits”, pp. 214-215, 1998, Symposium on VLSI Circuits Digest of Technical Papers discloses such a signal interpolation circuit. An example of the disclosed signal interpolation circuit is shown in FIG. 23. A signal interpolation circuit 62e, for example, has two input terminals x1 and x2 and nine output terminals y1 through y9. When the signal interpolation circuit 62e receives signals Va and Vb having a different phase from each other from the input terminals X1 and X2, respectively, as shown in FIG. 24A, the signal interpolation circuit 62e outputs a pair of output signals Vk′ and Vs′ having phases similar to those of the input signals Va and Vb, respectively, and seven interpolation signals Vl′ through Vr′ spaced equally in phase between the pair of output signals Vk′ and Vs′ from the output terminals y1 through y9, respectively, as shown in FIG. 24B.
FIG. 25 is a circuit diagram illustrating a specific configuration of the signal interpolation circuit 62e. The signal interpolation circuit 62e shown in FIG. 25 includes a pair of inverters 41 and 42 and a first interpolation processor portion 10. The inverters 41 and 42 receive signals Va and Vb input from input terminals X1 and X2, respectively. The first interpolation processor portion 10 interpolates signals Va′ and Vb′ output from the inverters 41 and 42, respectively, and outputs a pair of output signals Vc and Ve having phases similar to those of the input signals Va′ and Vb′, respectively, and an interpolation signal Vd having a phase intermediate between the signals Vc and Ve.
The signals Vc through Ve output from the first interpolation processor portion 10 are input to three inverters 43, 44, and 45, respectively. The inverters 43, 44, and 45 output signals Vc′ through Ve′, respectively, to a second interpolation processor portion 20. The second interpolation processor portion 20 interpolates the signals Vc′ through Ve′ and outputs five signals Vf, Vg, Vh, Vi, and Vj. Specifically, the pair of signals Vc′ and Vd′ and the pair of signals Vd′ and Ve′ are subjected to interpolation similar to that in the first interpolation processor portion 10.
The signals Vf through Vj output from the second interpolation processor portion 20 are input to five inverters 46, 47, 48, 49, and 50, respectively. Output signals Vf′ through Vj′ of the inverters 46 through 50, respectively, are input to a third interpolation processor portion 30. The third interpolation processor portion 30 interpolates the signals Vf′ through Vj′ and outputs nine signals Vk, Vl, Vm, Vn, Vo, Vp, Vq, Vr, and Vs. Specifically, the pair of signals Vf′ and Vg′, the pair of signals Vg′ and Vh′, the pair of signals Vh′ and Vi′, and the pair of signals Vi′ and Vj′ are subjected to interpolation similar to that in the first interpolation processor portion 10. The nine interpolating signals Vk through Vs output from third interpolation processor portion 30 are input to nine inverters 51 through 59, respectively. Outputs of the inverters 51 through 59 are output from output terminals y1 through y9 as output signals Vk′ thorough Vs′, respectively.
The first interpolation processor portion 10 includes a pair of first circuit blocks 11, a common second circuit block 12, and a pair of second circuit blocks 12. The pair of first circuit blocks 11 receive the outputs Va′ and Vb′ of the inverters 41 and 42, respectively. The common second circuit block 12 receives the outputs Va′ and Vb′ of the inverters 41 and 42, respectively. The pair of second circuit blocks 12 receive the outputs Va′ and Vb′ of the inverters 41 and 42, respectively.
Each first circuit block 11 has a similar configuration which includes a single inverter 11a as shown in FIG. 26A. All the second circuit blocks 12 as well as the common second circuit block 12 have a similar configuration which includes a pair of inverters 12a as shown in FIG. 26B. The common second circuit block 12 outputs a combination of outputs of the pair of inverters 12a. 
As shown in FIG. 27, the outputs Va′ and Vb′ of the inverters 41 and 42, respectively, are input to the respective first circuit blocks 11, and are inverted to the output signals Vc and Ve. Outputs of the inverters 41 and 42 are input to the respective inverters 12a of the common second circuit block 12. A combination of the outputs of both the inverters 12a is the output Vd of the common second circuit block 12. The outputs Vc and Ve of the first circuit block 11 and the output Vd of the common second circuit block 12 are inverted by the inverters 43 and 45, and 44, respectively, to be output into the second interpolation processor portion 20.
In the second interpolation processor portion 20, the output signal Vc′ of the inverter 43 and the output Vd′ of the inverter 44 are input to the respective first circuit blocks 11 and a single common second circuit block 12. The outputs Vf and Vh are output from the respective first circuit blocks 11. The output Vg is output from the common second circuit block 12. The output signal Vd′ of the inverter 44 and the output Ve′ of the inverter 45 are input to the respective first circuit blocks 11 and a single common second circuit block 12. The outputs Vh and Vj are output from the respective first circuit blocks 11. The output Vi is output from the common second circuit block 12. The outputs Vf through Vj are input to the inverters 46 through 50. The inverters 46 through 50 output the signals Vf′ through Vj′, respectively.
In the third interpolation process or portion 30, the output signals Vf′ through Vj′ from the inverters 46 through 50 are input to the respective first circuit blocks 11. An output signal of each pair of adjacent inverters (46 and 47, 47 and 48, 48 and 49, and 49 and 50) is input to a common second circuit block 12. The five first circuit blocks 11 output the signals Vk, Vm, Vo, Vq, and Vs, respectively. The four common second circuit blocks 12 output the signals Vl, Vn, Vp, and Vr. The output signals Vk through Vs are input to the inverters 51 through 59 which output the interpolating signals Vk′ through Vs′, respectively.
The circuit size of each inverter 11a included in the first circuit block 11 is designed to be substantially equal to the total of the circuit size of each pair of inverters 12a included in the common second circuit block 12. For this reason, as shown in FIG. 5, the inverters 43 and 44 into which the outputs Vc and Ve from the first circuit block 11 are input, respectively, each have a load equal to that of the inverter 45 into which the output Vd from the common second circuit block 12 is input. The signals Va′ and Vb′ output from the inverters 41 and 42 have the same propagation time by the time of being output from the inverters 43 through 45 as the signals Vc′ through Ve′, respectively.
In the first interpolation processor portion 10, a pair of first circuit blocks 11 and a single second circuit block 12 are included in a signal interpolation circuit. A pair of input signals Va′ and Vb′ output from the inverters 41 and 42 have the same propagation time by the time of being output from the inverters 43 through 45 as the three signals Vc′ through Ve′, respectively.
In the second interpolation processor portion 20, a pair of first circuit blocks 11 and a single second circuit block 12 are included in a signal interpolation circuit. In each interpolation circuit block, input signals have the same propagation time from input to output. The three signals Vc′ through Ve′ output from the inverters 43 through 45 have the same propagation time by the time of being output from the inverters 46 through 50 as the five signals Vf′ through Vj′, respectively.
In the third interpolation processor portion 30, a pair of first circuit blocks 11 and a single second circuit block 12 are included in a signal interpolation circuit. The five signals Vf′ through Vj′ output from the inverters 46 through 50 have the same propagation time by the time of being output from the nine inverters 51 through 59 as the signals Vk′ through Vs′, respectively.
The inverters 11a and 12a in each signal interpolation circuit invert the level of an output signal when an input signal goes to a state which is higher than a predetermined threshold voltage Vth from a lower state, or when the input signal goes to the lower state from the higher state. As shown in FIG. 28A, when the output Vd of the common second circuit block 12 is input to the inverter 44, the input signal Vd goes from the state which is higher than the threshold voltage Vth to the lower state and the level of the output signal of the inverter 44 is inverted. Therefore, the output signal Vd′ of the inverter 44 ideally has a phase intermediate between those of the signals Vc′ and Ve′ output from the inverters 43 and 45 as shown in FIG. 28B.
However, the threshold voltage Vth of the inverter is set in an appropriate voltage range. The output Vd of the common second circuit block 12 has a state in which there is substantially no change in a voltage for an appropriate time as shown in FIG. 28C. For this reason, the signal Vd′ does not have an intermediate phase which does not space equally in phase between the signals Vc′ and Ve′ output from the inverters 43 and 45. A pair of signals having a phase difference is unlikely to be linearly interpolated.